Read-only memory (rom) device structure and method for forming the same

ABSTRACT

A read-only memory (ROM) structure is provided. The ROM device structure includes a first gate structure formed over a substrate, and the first gate structure includes a first work function layer with a first thickness. The ROM device structure includes an isolation structure formed over the substrate, and the isolation structure is adjacent to the first gate structure. The isolation structure includes a second work function layer with a second thickness, and the second thickness is larger than or smaller than the first thickness. The ROM device structure also includes a first contact structure formed over the substrate, and the first contact structure is between the first gate structure and the isolation structure.

CROSS REFERENCE TO RELATED APPLICATIONS

This Application claims the benefit of U.S. Provisional Application No.62/344,226, filed on Jun. 1, 2016, and entitled “Read-only memory (ROM)device structure and method for forming the same”, the entirety of whichis incorporated by reference herein. This application is a Continuationapplication of U.S. patent application Ser. No. 15/261,282, filed onSep. 9, 2016, the entire of which is incorporated by reference herein.

BACKGROUND

Semiconductor devices are used in a variety of electronic applications,such as personal computers, cell phones, digital cameras, and otherelectronic equipment. Semiconductor devices are typically fabricated bysequentially depositing insulating or dielectric layers, conductivelayers, and semiconductive layers of material over a semiconductorsubstrate, and patterning the various material layers using lithographyto form circuit components and elements thereon. Many integratedcircuits are typically manufactured on a single semiconductor wafer, andindividual dies on the wafer are singulated by sawing between theintegrated circuits along a scribe line. The individual dies aretypically packaged separately, in multi-chip modules, for example, or inother types of packaging.

A read-only memory (ROM) device structure is a nonvolatile semiconductormemory device which is widely utilized in digital electronicsapplications. The data stored in the ROM device structure can beretained permanently even after the power is turned off.

Although existing ROM devices and methods of fabricating ROM deviceshave generally been adequate for their intended purposes, they have notbeen entirely satisfactory in all respects.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It shouldbe noted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIG. 1 shows a circuit diagram of a read-only memory (ROM) cell array,in accordance with some embodiments of the disclosure.

FIG. 2 shows a layout diagram of a read-only memory (ROM) cell array, inaccordance with some embodiments of the disclosure.

FIGS. 3A-3L show cross-sectional representations of various stages offorming read-only memory (ROM) cell array shown in FIG. 2, in accordancewith some embodiments of the disclosure.

FIGS. 4A-4D show cross-sectional representations of various stages offorming read-only memory (ROM) cell array shown in FIG. 2, in accordancewith some embodiments of the disclosure.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the subject matterprovided. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Some variations of the embodiments are described. Throughout the variousviews and illustrative embodiments, like reference numbers are used todesignate like elements. It should be understood that additionaloperations can be provided before, during, and after the method, andsome of the operations described can be replaced or eliminated for otherembodiments of the method.

Embodiments for forming a read-only memory (ROM) cell device structureare provided. FIG. 1 shows a circuit diagram of a read-only memory (ROM)cell array 100, in accordance with some embodiments of the disclosure.The ROM cell array 100 includes a number of rows and a number ofcolumns. The ROM cell array 100 includes four word lines WY-Y+3, WY-Y+2,WY-Y+1 and WY-Y, two bit lines BL-X and BL-X+1, and two groundpotentials GND. The ROM cell array 100 is addressed by word linesWY-Y+3, WY-Y+2, WY-Y+1 and WY-Y. Other circuit (e.g. controller) canaccess ROM cell array 100 through the word lines and bit lines BL-X andBL-X+1.

The ROM cell array 100 includes a first transistor 12, a secondtransistor 14, a third transistor 16, a fourth transistor 18, a firstisolation transistor 21, a second isolation transistor 23 and a thirdisolation transistor 25. The gate terminals of the first transistor 12,the second transistor 14, the third transistor 16 and the fourthtransistor 18 are biased from the word lines WY-Y+3, WY-Y+2, WY-Y+1 andWY-Y. A reading voltage for activating the first transistor 12, thesecond transistor 14, the third transistor 16 and the fourth transistor18 is provided through the word lines WY-Y+3, WY-Y+2, WY-Y+1 and WY-Y.The drain terminal of the first transistor 12 is biased from the bitline BL-X. The source terminal of the first transistor 12 iselectrically connected to the ground potential GND.

The gate terminals of the first isolation transistor 21, the secondisolation transistor 23 and the third isolation transistor 25 areelectrically connected to the ground potential GND. In a first bit cell,a first group of transistors includes at least two transistors, such asthe first transistor 12 and the second transistor 14. In a second bitcell, a second group of transistors includes at least two transistors,such as the third transistor 16 and the fourth transistor 18. The secondisolation transistor 23 is formed between the first bit cell and thesecond bit cell. More specifically, the second isolation transistor 23is formed between the first group of transistors and the second group oftransistors. The first isolation transistor 21, the second isolationtransistor 23, and the third isolation transistor 25 are configured toelectrically isolate the adjacent transistors which belong to differentbit cells.

In the right side of FIG. 1, the layout of the first column is similarto that of the second column. Another four transistors 32,34,36,38 areformed next to the transistors 12,14,16,18 and two isolation transistors41, 43, 45 are next to the isolation transistors 23, 25. The drainterminal of another four transistors 32,34,36,38 are biased from the bitline BL-X+1. The gate terminals of another four transistors 32,34,36,38are electrically connected to the ground potential GND.

FIG. 2 shows a layout diagram of a read-only memory (ROM) cell array100, in accordance with some embodiments of the disclosure. The ROM cellarray 100 includes a first continuous region 10 and a second continuousregion 20. In some other embodiments, the first continuous region 10 hasa first-type conductivity (e.g. n-type or p-type), and the secondcontinuous region 20 has the same-type conductivity. In some otherembodiments, the first continuous region 10 has a first-typeconductivity (e.g. n-type or p-type), and the second continuous region20 has a second-type conductivity opposite to the first-typeconductivity.

The first continuous region 10 and the second continuous region 20 areformed over a substrate 102 (shown in FIG. 3A). The substrate 102 may bemade of silicon or other semiconductor materials. Alternatively oradditionally, the substrate 102 may include other elementarysemiconductor materials such as germanium. In some embodiments, thesubstrate 102 is made of a compound semiconductor such as siliconcarbide, gallium arsenic, indium arsenide, or indium phosphide. In someembodiments, the substrate 102 is made of an alloy semiconductor such assilicon germanium, silicon germanium carbide, gallium arsenic phosphide,or gallium indium phosphide. In some embodiments, the substrate 102includes an epitaxial layer. For example, the substrate 102 has anepitaxial layer overlying a bulk semiconductor. The bulk semiconductormay be silicon, germanium, or other suitable materials.

The first continuous region 10 and the second continuous region 20 canreduce or eliminate the use of isolation structures, such as a shallowtrench isolation (STI) region. Therefore, the stress on the substratemay be reduced.

The first continuous region 10 and a second continuous region 20 aresurrounded by an isolation region 30. In other words, the firstcontinuous region 10 is insulated from the second continuous region 20by the isolation region 30. In some embodiments, the isolation region 30is the shallow trench isolation (STI) region.

The ROM cell array 100 further includes a number of word lines 204 and anumber of isolation lines 206. The word lines 204 are shown ashorizontal lines and labeled as WL-Y, WL-Y+1, WL-Y+2 and WL-Y+3.

The isolation lines 206 are shown as horizontal lines disposed betweenadjacent word lines 204. For example, the isolation lines 206 aredisposed between the word lines WL-Y+1 and WL-Y+2, below the word lineWL-Y and above the word line WL-Y+3.

The ROM cell array 100 further includes a number of bit lines 212, and anumber of ground potential (V_(SS)) lines 214. The bit lines 212 areshown as vertical lines and labeled as BL-X and BL-X+1. The bit lines212 are orthogonal to the word lines 204. The V_(SS) lines 214 are shownas vertical lines and are orthogonal to the word lines 204. In someembodiments, the bit lines 212 are formed in a first metal layer (M₁)(shown in FIG. 3K) and connected to a second metal layer (M₂) viaconductive vias 180.

The isolation transistors 21, 23, 25 controlled by the isolation lines206 remain at all times in the “off” state. In some embodiments, theisolation structure 144 a (shown in FIG. 3K) is the P-type MOS device,and the isolation lines 206 is electrically connected to the voltagesupply (Vdd) of the PMOS device. In some embodiments, the isolationstructure 144 a (shown in FIG. 3K) is the N-type MOS device, and theisolation lines 206 is electrically connected to the ground potential(GND) of the NMOS device.

The ROM cell array 100 includes four bit cell regions 52, 54, 56 and 58.The first bit cell region 52 includes two word lines 204 (also calledWL-Y+3 and WL-Y+2), half of the isolation line 206 which is above theword line WL-Y+3, and half of the isolation line 206 which is below theword line WL-Y+2. The second bit cell region 54 includes two word lines204 (also called WL-Y and WL-Y+1), half of the isolation line 206 whichis above the word line WL-Y, and half of the isolation line 206 which isbelow the word line WL-Y+1. The isolation transistors 21, 23, 25, whichremain at all times in the “off” state, are provided between thetransistors in two adjacent bit cell regions to reduce leakage currentthere-between.

As shown in FIG. 2, the isolation line 206 is formed between the firstgroup of word lines 204 in the first bit cell region 52 and the secondgroup of word lines 204 in the second bit cell region 54. The word lines204 and the isolation line 206 are formed in the same metal layer, suchas second metal layer (M₂). The bit lines 212 and V_(SS) lines 214 areformed in the first metal layer (M₁) below the second metal layer (M₂).The bit lines 212 in the first metal layer (M₁) are connected to theword lines 204 in the second metal layer (M₂) through via 116.

FIGS. 3A-3K show cross-sectional representations of various stages offorming read-only memory (ROM) cell array 100 shown in FIG. 2, inaccordance with some embodiments of the disclosure. FIG. 3A is across-sectional representation along the line AA′ in FIG. 2.

As shown in FIG. 3A, an active region 104 is formed over the substrate102. The active region 104 is formed from the substrate 102 and may haveN-type conductivity or P-type conductivity.

Instead of using the STI isolation structure, the isolation transistors21, 23, 25 are configured to provide isolation between adjacenttransistors. Accordingly, the active region 104 eliminates the use of anSTI isolation structure between two transistor device structures. Theactive region 104 includes the first bit cell region 52 and the secondbit cell region 54. A number of dummy gate structures 106 are formedover the active region 104. In some embodiments, the dummy gatestructures 106 are made of polysilicon.

After the dummy gate structures 106 are formed, spacers 108 are formedover the opposite sidewalls of the dummy gate structures 106, as shownin FIG. 3B in accordance with some embodiments of the disclosure. Thespacers 108 may be a single layer or multiple layers. The spacers 108are formed by deposition processes, such as a chemical vapor deposition(CVD) process, high-density plasma chemical vapor deposition (HDPCVD)process, spin-on process, sputtering process, or another applicableprocess.

Afterwards, the source/drain (S/D) structures 110 are formed in theactive region 104. In some embodiments, the source/drain (S/D)structures 110 are epitaxial structures and they are formed by anepitaxial (epi) process. In some embodiments, the source/drain (S/D)structures 110 include Ge, SiGe, InAs, InGaAs, InSb, GaAs, GaSb, InAlP,InP, or the like.

After the source/drain (S/D) structures 110 are formed, an inter-layerdielectric (ILD) structure 112 is formed over the dummy gate structures106 and the active region 104, as shown in FIG. 3C in accordance withsome embodiments of the disclosure.

The ILD structure 112 may include multilayers made of multipledielectric materials, such as silicon oxide, silicon nitride, siliconoxynitride, tetraethoxysilane (TEOS), phosphosilicate glass (PSG),borophosphosilicate glass (BPSG), low-k dielectric material, and/orother applicable dielectric materials. Examples of low-k dielectricmaterials include, but are not limited to, fluorinated silica glass(FSG), carbon doped silicon oxide, amorphous fluorinated carbon,parylene, bis-benzocyclobutenes (BCB), or polyimide.

The ILD material 112 is formed by a deposition process, such as chemicalvapor deposition (CVD), physical vapor deposition, (PVD), atomic layerdeposition (ALD), spin-on coating, or another applicable process.Afterwards, a polishing process is performed to the ILD structure 112until the top surfaces of the dummy gate structures 106 are exposed. Insome embodiments, the ILD structure 112 is planarized by a chemicalmechanical polishing (CMP) process.

Afterwards, the dummy gate structures 106 are removed to form a numberof trenches 114, as shown in FIG. 3D in accordance with some embodimentsof the disclosure. In some embodiments, the dummy gate structures 106are removed by a wet etching process or a dry etching process.

Afterwards, a gate dielectric layer 120 is conformally formed in thetrench 114 as shown in FIG. 3E, in accordance with some embodiments.More specifically, the gate dielectric layer 120 is formed over bottomsurfaces and sidewalls of the trenches 114, and over the inter-layerdielectric (ILD) structure 112.

The gate dielectric layer 120 may be a single layer or multiple layers.The gate dielectric layer 120 is made of silicon oxide (SiOx), siliconnitride (SixNy), silicon oxynitride (SiON), dielectric material(s) withhigh dielectric constant (high-k), a combination thereof, or othersuitable material. Examples of high-k dielectric materials includehafnium oxide, zirconium oxide, aluminum oxide, hafnium dioxide-aluminaalloy, hafnium silicon oxide, hafnium silicon oxynitride, hafniumtantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, thelike, or a combination thereof, or other suitable material.

Afterwards, a first material 122 is conformally formed in the trench 114and over the gate dielectric layer 120, as shown in FIG. 3F, inaccordance with some embodiments. The first material 122 is configuredto adjust the work function value of the gate structure of thetransistor device. The thickness of the work function layer affects thethreshold voltage (Vth) of the transistor. In some embodiments, when aPMOSFET device with a thinner work function layer is used as theisolation structure, the PMOSFET device may exhibit a higher thresholdvoltage. In other embodiments, when the NMOSFET device with thicker workfunction layer is used as the isolation structure, the NMOSFET devicewill have a higher threshold voltage.

In some embodiments, the first material 122 is made of P-typeconductivity materials including titanium nitride (TiN), tantalumnitride (TaN), ruthenium (Ru), molybdenum (Mo), aluminum (Al), tungstennitride (WN), zirconium disilicide (ZrSi₂), molybdenum disilicide(MoSi₂), tantalum silicide (TaSi₂), nickel silicide (NiSi₂), othersuitable p-type work function materials, or a combination thereof, orother suitable material. In some other embodiments, the first material122 is made of N-type conductivity materials including titanium (Ti),silver (Ag), tantalum aluminum (TaAl), tantalum aluminum carbide(TaAlC), titanium aluminum nitride (TiAlN), tantalum carbide (TaC),tantalum carbide nitride (TaCN), tantalum silicon nitride (TaSiN),manganese (Mn), zirconium (Zr), other suitable n-type work functionmaterials, or a combination thereof, or other suitable material.

In some embodiments, the first material 122 is formed by a depositionprocess, such as chemical vapor deposition (CVD), physical vapordeposition, (PVD), atomic layer deposition (ALD), spin-on coating, oranother applicable process. In some embodiments, the first material 122has a first thickness T₁.

After the first material 122 is formed, a mask 124 is disposed on thefirst material 122 and patterned to form a patterned mask 124 covering aportion of the first material 122, as shown in FIG. 3G, in accordancewith some embodiments. The mask 124 is configured to protect theunderlying layers from being removed by the subsequent processes.Afterwards, a portion of the first material 122 is selectively removedto expose the trenches 125. In some embodiments, the portion of thefirst material 122 is removed by a dry etching process or a wet etchingprocess.

Afterwards, the mask 124 is removed, and a second material 126 is formedover the first material 122 and in the trenches 125, as shown in FIG.3H, in accordance with some embodiments. The first material 122 isdifferent from the second material 126. The second material 126 is alsoconfigured to adjust the work function value of the gate structure ofthe transistor device.

In some embodiments, the second material 126 is made of P-typeconductivity materials including titanium nitride (TiN), tantalumnitride (TaN), ruthenium (Ru), molybdenum (Mo), aluminum (Al), tungstennitride (WN), zirconium disilicide (ZrSi₂), molybdenum disilicide(MoSi₂), tantalum silicide (TaSi₂), nickel silicide (NiSi₂), othersuitable p-type work function materials, or a combination thereof, orother suitable material. In some other embodiments, the second material126 is made of N-type conductivity materials including titanium (Ti),silver (Ag), tantalum aluminum (TaAl), tantalum aluminum carbide(TaAlC), titanium aluminum nitride (TiAlN), tantalum carbide (TaC),tantalum carbide nitride (TaCN), tantalum silicon nitride (TaSiN),manganese (Mn), zirconium (Zr), other suitable n-type work functionmaterials, or a combination thereof, or other suitable material. In someembodiments, the second material 126 has a second thickness T₂.

After the second material 126 is formed, a metal gate electrode layer128 is formed over the second material 126, as shown in FIG. 3I, inaccordance with some embodiments.

In some embodiments, the metal gate electrode layer 128 is made ofconductive material, such as aluminum (Al), copper (Cu), tungsten (W),titanium (Ti), tantalum (Ta), or another applicable material. The metalgate electrode layer 128 is formed by a deposition process, such aschemical vapor deposition (CVD), physical vapor deposition (PVD), atomiclayer deposition (ALD), high density plasma CVD (HDPCVD), metal organicCVD (MOCVD), or plasma enhanced CVD (PECVD).

Afterwards, the excess metal gate electrode materials are removed by apolishing process, as shown in FIG. 3J, in accordance with someembodiments. As a result, the top surface of the metal gate electrodelayer 128 and the top surface of the ILD structure 112 are exposed. Inother words, the top surface of the metal gate electrode layer 128 isplanar with the top surface of the ILD structure 112. In someembodiments, the polishing process is a chemical mechanical polishing(CMP) process.

As shown in FIG. 3J, a first gate structure 142 a and a second gatestructure 142 b are formed in the first bit cell region 52, and thethird gate structure 142 c and the fourth gate structure 142 d areformed in the second bit cell region 54. A first isolation structure 144a is adjacent to the first gate structure 142 a. A second isolationstructure 144 b is formed between the second gate structure 142 b andthe third gate structure 142 c. A third isolation structure 144 c isformed adjacent to the fourth gate structure 142 d.

The first group of gate structures including at least two gatestructures 142 a, 142 b is formed in the first bit cell region 52, andthe second group of gate structures including at least two gatestructures 142 a, 142 b is formed in the second bit cell region 54. Theisolation structure 144 b is formed between the first group of gatestructures and the second group of gate structures.

It should be noted that the gate structures 142 a, 142 b, 142 c and 142d are functional or operational gate structures, but the isolationstructures 144 a, 144 b and 144 c are dummy structures which do notperform any function. As mentioned above, the isolation structures 144a, 144 b, and 144 c controlled by the isolation lines 206 (shown in FIG.2) remain at all times in the “off” state. The isolation structures 144a, 144 b and 144 c are electrically connected to the isolation lines206, and remain at all times in the “off” state.

Half of the second isolation structure 144 b belongs to the first bitcell region 52, and half of the second isolation structure 144 b belongsto the second bit cell region 54. In other words, the second isolationstructure 144 b is at the boundary between the first bit cell region 52and the second bit cell region 54.

The first gate structure 142 a includes the gate dielectric layer 120,the first work function layer made of the second material 126 and themetal gate electrode layer 128. The first isolation structure 144 aincludes the gate dielectric layer 120, the second work function layermade of the first material 122 and the second material 126, and themetal gate electrode layer 128. Therefore, the first work function layerof the first gate structure 142 a has a thickness T₂, and the secondwork function layer of the first isolation structure 144 a has a sumthickness T₃ of the first thickness T₁ and the second thickness T₂. Thesum thickness T₃ is larger than the thickness T₂.

In some embodiments, the first work function layer of the first gatestructure 142 a is made of the second material 126, and therefore thefirst gate structure 142 a has a first-type conductivity. The secondwork function layer of the first isolation structure 144 a is made ofthe first material 122 and the second material 126, and therefore thefirst isolation structure 144 a has a second-type conductivity oppositeto the first-type conductivity. In some embodiments, the first workfunction layer of the first gate structure 142 a is N-type transistor,and the second work function layer of the first isolation structure 144a is P-type transistor.

It should be noted that the threshold voltage (Vth) difference betweenthe first isolation structure 144 a and the first gate structure 142 ais caused by the thickness difference (ΔT=T₃−T₂) between the workfunction layer of the first isolation structure 144 a and the workfunction layer of the first gate structure 142 a. The advantage of thethreshold voltage (Vth) difference is that the leakage current betweentwo gate structures in adjacent bit cell regions may be reduced. Inother words, the work function value of the gate structure is affectedby changing the thickness of the work function layer. The thresholdvoltage (Vth) is affected by the work function value. Therefore, thethreshold voltage (Vth) is affected by changing the thickness of thework function layer of the gate structure. In addition, the leakagecurrent is reduced when the transistor has a higher threshold voltage(Vth). Accordingly, when the isolation structure 114 a has a higherthreshold voltage (Vth) than the adjacent first gate structure 142 a,the leakage current is reduced by the isolation structure 114 a.Therefore, the performance of the gate structure is improved when theleakage current is reduced.

In some embodiments, the thickness difference (ΔT=T₃−T₂) is in a rangefrom about 1 nm to 3 nm. If the thickness difference ΔT is smaller than1 nm, the leakage current suppression effect is not good enough. If thethickness difference ΔT is greater than 3 nm, the metal gate electrodelayer 128 is hardly to filled into the trench which is used to form thegate structure.

In some embodiments, the threshold voltage (Vth) difference is in arange from about 100 mV to about 500 mV. If the threshold voltage (Vth)difference is smaller than 100 mV, the leakage current suppressioneffect is not good enough. If the threshold voltage (Vth) difference isgreater than 500 mV, the performance of the gate structures may suffer.

After the polishing process, an interconnect structure 160 is formedover the gate structures 142 a, 142 b, 142 c and 142 d, and theisolation structures 144 a, 144 b and 144 c, as shown in FIG. 3K, inaccordance with some embodiments. A dielectric layer 152 is formed overthe gate structures 142 a, 142 b, 142 c and 142 d, and the isolationstructures 144 a, 144 b, 144 c. The contact structures 150 a, 150 b, 150c, 150 d, 150 e, 150 f are formed through the dielectric layer 152 andthe ILD structure 112. The vias 162 are formed over the top surfaces ofthe gate structures 142 a, 142 b, 142 c and 142 d, and the top surfacesof the isolation structures 144 a, 144 b, 144 c.

The contact structures 150 a, 150 b, 150 c, 150 d, 150 e, 150 f areelectrically connected to the S/D structure 110 in the active region104. The top surface of the contact structures 150 a, 150 b, 150 c, 150d, 150 e, 150 f are higher than the top surface of the gate structures142 a, 142 b, 142 c and 142 d.

The first contact structure 150 a, the second contact structure 150 band the third contact structure 150 c are formed in the first bit cellregion 52, and the second contact structure 150 b is formed between thefirst contact structure 150 a and the third contact structure 150 c. Thefourth contact structure 150 d, the fifth contact structure 150 e andthe sixth contact structure 150 f are formed in the second bit cellregion 54, and the fifth contact structure 150 e is formed between thefourth contact structure 150 d and the sixth contact structure 150 f.

The first contact structure 150 a is formed between the first isolationstructure 144 a and the first gate structure 142 a. In some embodiments,the first contact structure 150 a is electrically connected to the bitlines 212 (shown in FIG. 2). The third contact structure 150 c is formedbetween the second gate structure 142 b and the second isolationstructure 144 b. In some embodiments, the third contact structure 150 cis electrically connected to the bit lines 212 (shown in FIG. 2).

The second contact structure 150 b is formed between the first gatestructure 142 a and the second gate structure 142 b. In someembodiments, the second contact structure 150 b is electricallyconnected to the ground potential (Vss). The second contact structure150 b is configured to isolate the first gate structure 142 a and thesecond gate structure 142 b.

The fourth contact structure 150 d is electrically connected to the bitlines 212 (shown in FIG. 2). The fifth contact structure 150 e iselectrically connected to the ground potential (Vss). The sixth contactstructure 150 f is electrically connected to the bit lines 212 (shown inFIG. 2).

Afterwards, the first metal layer 164, the second metal layer 166 andthe vias 162 are formed over the contact structure 150 a, 150 b, 150 c,150 d, 150 e, 150 f a and over the gate structures 142 a, 142 b, 142 cand 142 d, and the isolation structures 144 a, 144 b, 144 c, as shown inin FIG. 3L, in accordance with some embodiments.

The interconnect structure 160 includes the first metal layer 164, thesecond metal layer 166 and vias 162 formed in a dielectric layer 170. Insome embodiments, the first metal layer 164, the second metal layer 166and vias 162 are made of conductive materials, such as copper (Cu),copper alloy, aluminum (Al), aluminum alloys or a combination thereof,or other suitable material. In some embodiments, the first metal layer164, the second metal layer 166 and vias 162 are copper (Cu) or copperalloy. In some embodiments, the interconnect structure 160 is formed ina back-end-of-line (BEOL) process. In some embodiments, the first metallayer 164, the second metal layer 166 and vias 162 are formed by singleand/or dual damascene processes. The metal layers 164, 166 includemultiple metal layers (namely M₁, M₂, M₃ . . . , and Mtop) which areinterconnected through vias 162.

It should be noted that in some embodiments, the bit lines 212 and theV_(SS) lines 214 (shown in FIG. 2) are formed in the first metal layer(M₁) 164. The word lines 204 and the isolation lines 206 are formed inthe second metal layer (M₂) 166.

The metal routings of the conductive features as shown in FIG. 3L, aremerely examples. Alternatively, other designs of metal routings ofconductive features may be used according to actual application.

FIGS. 4A-4D show cross-sectional representations of various stages offorming the read-only memory (ROM) cell array 100 shown in FIG. 2, inaccordance with alternative embodiments in accordance with the instantdisclosure. FIG. 4A is a cross-sectional representation along the lineAA′ in FIG. 2. Processes and materials used to form the ROM devicestructure in FIGS. 3A-3L may be similar to, or the same as, those usedto form the ROM device structure in FIGS. 4A-4D and are not repeatedherein.

As shown in FIG. 4A, the mask layer 124 is formed over a portion of thefirst material 122. Afterwards, a portion of the first material 122which is not protected by the mask layer 124 is removed by an etchingprocess.

Afterwards, the mask layer 124 is removed, and the second material 126is formed over the first material 122 and the gate dielectric layer 120,as shown in in FIG. 4B, in accordance with some embodiments.

After the second material 126 is formed, the metal gate electrode layer128 is formed over the second material 126, as shown in FIG. 4C, inaccordance with some embodiments.

Afterwards, the first gate structure 142 a and the second gate structure142 b are formed in the first bit cell region 52, and the third gatestructure 142 c and the fourth gate structure 142 d are formed in thesecond bit cell region 54, as shown in FIG. 4D, in accordance with someembodiments. The first isolation structure 144 a is adjacent to thefirst gate structure 142 a. The second isolation structure 144 b isformed between the second gate structure 142 b and the third gatestructure 142 c.

It should be noted that the first work function layer of the first gatestructure 142 a has a sum thickness T₃ which is the sum of the firstthickness T₁ and the second thickness T₂. The second work function layerof the first isolation structure 144 a has a thickness T₂. The ROMdevice structure has leakage current suppression function by forming thethickness difference between the gate structure and the isolationstructure.

Embodiments for a read-only memory (ROM) device structure and method forformation the same are provided. The ROM device structure includes anisolation structure between two groups of gate structures. The isolationstructure is configured to isolate a first group of gate structures anda second group of gate structures. A threshold voltage (Vth) differencebetween the gate structure and the isolation structure is caused byforming the thickness difference between a thickness of a work functionlayer of the gate structure and that of a work function layer of theisolation structure. The isolation structure with a higher thresholdvoltage (Vth) has a relatively lower leakage current. Accordingly, theleakage current is suppressed by adjusting the thickness difference ofthe gate structure and the isolation structure, and therefore theperformance of the ROM device structure is improved.

In some embodiments, a read-only memory (ROM) device structure isprovided. The ROM device structure includes a first gate structureformed over a substrate, and the first gate structure comprises a firstwork function layer with a first thickness. The ROM device structureincludes an isolation structure formed over the substrate, and theisolation structure is adjacent to the first gate structure. Theisolation structure includes a second work function layer with a secondthickness, and the second thickness is larger than or smaller than thefirst thickness. The ROM device structure also includes a first contactstructure formed over the substrate, and the first contact structure isbetween the first gate structure and the isolation structure.

In some embodiments, a read-only memory (ROM) device structure isprovided. The ROM device structure includes an active region over asubstrate and a first gate structure formed on the active region. Thefirst gate structure includes a first work function layer with afirst-type conductivity. The ROM device structure includes a firstisolation structure formed over the active region, and the firstisolation structure comprises a second work function layer with asecond-type conductivity. The first-type conductivity is different fromthe second-type conductivity. The ROM device structure further includesa second isolation structure formed over the active region, wherein thefirst gate structure is between the first isolation structure and thesecond isolation structure.

In some embodiments, a read-only memory (ROM) device structure isprovided. The ROM device structure includes an active region formed overa substrate and at least two gate structures formed over the activeregion. Each of the gate structures includes a first work functionlayer, and the first work function layer comprises a first material. TheROM device structure also includes an isolation structure formed overthe active region, wherein the isolation structure comprises a secondwork function layer, and the first work function layer includes thefirst material and a second material, the second material is differentfrom the first material.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A read-only memory (ROM) device structure,comprising: a first gate structure formed over a substrate, wherein thefirst gate structure comprises a first work function layer with a firstthickness; an isolation structure formed over the substrate, wherein theisolation structure is adjacent to the first gate structure, wherein theisolation structure comprises a second work function layer with a secondthickness, and the second thickness is larger than or smaller than thefirst thickness; and a first contact structure formed over thesubstrate, wherein the first contact structure is between the first gatestructure and the isolation structure.
 2. The read-only memory (ROM)device structure as claimed in claim 1, further comprising: aninterconnect structure formed over the first gate structure, the secondgate structure and the isolation structure, wherein the interconnectstructure comprises: a first metal layer formed over the first gatestructure, wherein the first contact structure is electrically connectedto the first metal layer; and a second metal layer formed over the firstmetal layer, wherein the first gate structure is electrically connectedto the second metal layer.
 3. The read-only memory (ROM) devicestructure as claimed in claim 1, wherein the first work function layerhas a first-type conductivity, and the second work function layer has asecond-type conductivity.
 4. The read-only memory (ROM) device structureas claimed in claim 1, wherein the substrate comprises an active region,and the active region is a continuous active region which is extendingunder the first gate structure, the second gate structure and theisolation structure.
 5. The read-only memory (ROM) device structure asclaimed in claim 1, further comprising: a second gate structure formedover the substrate; and a second contact structure formed between thesubstrate, wherein the second contact structure is between the firstgate structure and the second gate structure.
 6. The read-only memory(ROM) device structure as claimed in claim 1, wherein the isolationstructure is electrically connected to a ground potential (GND) or avoltage supply (Vdd).
 7. The read-only memory (ROM) device structure asclaimed in claim 1, wherein the first contact structure is electricallyconnected to a voltage supply (Vdd).
 8. The read-only memory (ROM)device structure as claimed in claim 1, wherein a top surface of thefirst contact structure is higher than a top surface of the first gatestructure.
 9. The read-only memory (ROM) device structure as claimed inclaim 1, further comprising: a third contact structure formed over thesubstrate, wherein the first gate structure is formed between the firstcontact structure and the third contact structure, the third contactstructure is electrically connected to a ground potential (GND).
 10. Theread-only memory (ROM) device structure as claimed in claim 1, furthercomprising: a source/drain (S/D) structure formed in the substrate anddirectly below the first contact structure, wherein the S/D structure isbetween the first gate structure and the isolation structure.
 11. Aread-only memory (ROM) device structure, comprising: an active regionover a substrate; a first gate structure formed on the active region,wherein the first gate structure comprises a first work function layerwith a first-type conductivity; a first isolation structure formed overthe active region, wherein the first isolation structure comprises asecond work function layer with a second-type conductivity, wherein thefirst-type conductivity is different from the second-type conductivity;and a second isolation structure formed over the active region, whereinthe first gate structure is between the first isolation structure andthe second isolation structure.
 12. The read-only memory (ROM) devicestructure as claimed in claim 11, further comprising: a first contactstructure formed over the active region, wherein the first contactstructure is adjacent to the first gate structure, and the first contactstructure is electrically connected to a ground potential (GND).
 13. Theread-only memory (ROM) device structure as claimed in claim 12, furthercomprising: a second contact structure formed over the active region,wherein the second contact structure is between the first isolationstructure and the second isolation structure.
 14. The read-only memory(ROM) device structure as claimed in claim 13, wherein the secondcontact structure is electrically connected to a voltage supply (Vdd).15. The read-only memory (ROM) device structure as claimed in claim 11,wherein the first isolation structure is electrically connected to aground potential (GND) or a voltage supply (Vdd).
 16. The read-onlymemory (ROM) device structure as claimed in claim 11, wherein a halfportion of the first isolation structure and the first gate structureare in a bit-cell region.
 17. The read-only memory (ROM) devicestructure as claimed in claim 11, wherein the first work function layerhas a first thickness, the second work function layer has a secondthickness, the first thickness is larger than or smaller than the secondthickness.
 18. A read-only memory (ROM) device structure, comprising: anactive region formed over a substrate; at least two gate structuresformed over the active region, wherein each of the gate structurescomprises a first work function layer, and the first work function layercomprises a first material; and an isolation structure formed over theactive region, wherein the isolation structure comprises a second workfunction layer, and the first work function layer comprises the firstmaterial and a second material, the second material is different fromthe first material.
 19. The read-only memory (ROM) device structure asclaimed in claim 18, wherein the first work function layer has afirst-type conductivity, and the second work function layer has asecond-type conductivity, wherein the first-type conductivity isdifferent from the second-type conductivity.
 20. The read-only memory(ROM) device structure as claimed in claim 18, further comprising: afirst contact structure formed over the substrate, wherein the firstcontact structure is between the gate structures and the isolationstructure.